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| 8-BIT SYNCHRONOUS BINARY UP COUNTER SY10E016 SY100E016 FEATURES s s s s s s s s 700MHz min. count frequency Extended 100E VEE range of -4.2V to -5.5V 1000ps CLK to Q, TC Internal, gated TC feedback 8 bits wide Fully synchronous counting and TC generation Asynchronous Master Reset Fully compatible with industry standard 10KH, 100K I/O levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E016 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E016 are high-speed synchronous, presettable and cascadable 8-bit binary counters designed for use in new, high-performance ECL systems. Architecture and operation are the same as the Motorola MC10H016 in the MECL 10KH family, extended to 8 bits, as shown in the logic diagram. The counters feature internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW, the TC feedback is disabled and counting proceeds continuously, with TC going LOW to indicate an all-HlGH state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. PIN CONFIGURATION VCCO PE CE P7 P6 P5 TC PIN NAMES Pin P0-P7 Q0-Q7 18 17 Function Parallel Data (Preset) Inputs Data outputs Count Enable Control Input Parallel Load Enable Control Input Master Reset Clock Terminal Count Output TC-Load Control Input VCC to Output 25 24 23 22 21 20 19 MR CLK TCLD VEE NC P0 P1 26 27 28 1 2 3 4 5 6 7 8 9 10 11 Q7 Q6 VCC Q5 VCCO Q4 Q3 CE PE MR CLK TC TCLD VCCO PLCC TOP VIEW J28-1 16 15 14 13 12 P2 P3 P4 VCCO Q0 Q1 Q2 Rev.: D Amendment: /2 1 Issue Date: May, 1998 Micrel SY10E016 SY100E016 BLOCK DIAGRAM TC Q7 BIT 7 P7 CE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q2 - Q6 5 5 Q1 BIT 1 P1 CE Q0 Q0 SLAVE Q0M Q0M MASTER BIT 0 BIT 2 - BIT 6 5 5 5 5 PE TCLD CE P0 MR CLK 2 Micrel SY10E016 SY100E016 TRUTH TABLE(1) CE X L L H X X PE L H H H X X TCLD X L H X X X MR L L L L L H CLK Z Z Z Z ZZ Z Function Load Parallel (Pn to Qn) Continuous Count Count; Load Parallel on TC = LOW Hold Master respond, Slaves Hold Reset (Qn : = LOW, TC : = HIGH) NOTE: 1. Z = Clock Pulse (LOW-to-HIGH), ZZ = Clock Pulse (HIGH-to-LOW) DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = -40C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 151 151 181 181 -- -- 151 151 181 181 -- -- 151 151 181 181 -- -- 151 174 181 208 Min. Typ. Max. Min. -- -- 150 -- TA = 0C Typ. -- TA = +25C TA = +85C Unit A mA Max. Min. Typ. Max. Min. Typ. Max. 150 -- -- 150 -- -- 150 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = -40C Symbol fCOUNT tPLH tPHL Parameter Max. Count Frequency Propagation Delay to Output CLK to Q MR to Q CLK to TC (Qs loaded)(1) CLK to TC (Qs unloaded)(1) MR to TC Set-up Time Pn CE PE TCLD Hold Time Pn CE PE TCLD Reset Recovery Time Minimum Pulse Width CLK, MR Rise/Fall Times 20% to 80% Min. Typ. Max. 700 600 600 550 550 625 150 600 600 500 250 0 0 100 900 400 300 900 725 775 775 700 775 -30 400 400 300 30 -400 -400 -300 700 -- 510 -- 1000 1000 1050 900 1000 -- -- -- -- -- -- -- -- -- -- 800 TA = 0C Min. Typ. Max. 700 600 600 550 550 625 150 600 600 500 250 0 0 100 900 400 300 900 725 775 775 700 775 -30 400 400 300 30 -400 -400 -300 700 -- 510 -- 1000 1000 1050 900 1000 -- -- -- -- -- -- -- -- -- -- 800 TA = 25C TA = +85C Unit MHz ps 600 600 550 550 625 150 600 600 500 250 0 0 100 900 400 300 725 775 775 700 775 -30 400 400 300 30 -400 -400 -300 700 -- 510 1000 1000 1050 900 1000 -- -- -- -- -- -- -- -- -- -- 800 600 600 550 550 625 150 600 600 500 250 0 0 100 900 400 300 725 775 775 700 775 -30 400 400 300 30 -400 -400 -300 700 -- 510 1000 1000 1050 900 1000 ps -- -- -- -- ps -- -- -- -- -- -- 800 ps ps ps Min. Typ. Max. Min. Typ. Max. 700 900 -- 700 900 -- tS tH tRR tWP tr tf NOTE: 1. CLK to TC propagation delay is dependent on the loading of the Q outputs. With all of the Q outputs loaded, the noise generated in going from a IIII IIII state to a 0000 0000 state causes the CLk to TC+ delay to increase. 3 Micrel SY10E016 SY100E016 FUNCTION TABLE Function Load Count PE L H H H H Load Hold L H H Load On Terminal Count H H H H H H Reset X CE X L L L L X H H L L L L L L X MR L L L L L L L L L L L L L L H TCLD CLK X L L L L X X X H H H H H H X Z Z Z Z Z Z Z Z Z Z Z Z Z Z X P7-P4 H X X X X H X X H H H H H H X P3 H X X X X H X X L L L L L L X P2 H X X X X H X X H H H H H H X P1 L X X X X L X X H H H H H H X P0 L X X X X L X X L L L L L L X Q7-Q4 H H H H L H H H H H H H H H L Q3 H H H H L H H H H H H L L H L Q2 H H H H L H H H H H H H H L L Q1 L L H H L L L L L H H H H L L Q0 L H L H L L L L H L H L H L L TC H H H L H H H H H H L H H H H 4 Micrel SY10E016 SY100E016 APPLICATIONS INFORMATION Cascading Multiple E016 Devices For applications which call for larger than 8-bit counters, multiple E016s can be tied together to achieve very wide bit width counters. The active low terminal count (TC) output and count enable input (CE) greatly facilitate the cascading of E016 devices. Two E016s can be cascaded without the need for external gating; however, for counters wider than 16 bits, external OR gates are necessary for cascade implementations. Figure 1, below, pictorially illustrates the cascading of 4 E016s to build a 32-bit high frequency counter. Note the E101 gates used to OR the terminal count outputs of the lower order E016s to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state), the more significant E016 is set in its count mode and will count one binary digit upon the next positive clock transition. In addition, the preceding devices will also count one bit, thus sending their terminal count outputs back to a high state, disabling the count operation of the more significant counters and placing them back into hold modes. Therefore, for an E016 in the chain to count all of the lower order terminal count outputs, it must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting E016 devices from Figure 1 and maintaining the logic pattern illustrated in the same figure. The maximum frequency of operation for the cascaded counter chain is set by the propagation delay of the TC output and the necessary set-up time of the CE input and the propagation delay through the OR gate controlling it (for 16bit counters the limitation is only the TC propagation delay and the CE set-up time). Figure 1 shows E101 gates used to control the count enable inputs; however, if the frequency of operation is lower, a slower ECL OR gate can be used. Using the worst case guarantees for these parameters from the ECLinPS data book, the maximum count frequency for a greater than 16-bit counter is 475MHz and that for a 16-bit counter is 625MHz. Note that this assumes the trace delay between the TC outputs and the CE inputs are negligible. If this is not the case, estimates of these delays need to be added to the calculations. LOAD Q0-Q7 "LO" Q0-Q7 Q0-Q7 Q0-Q7 CE PE CE PE CE PE CE PE E016 LSB E016 E016 E016 MSB CLK P0-P7 TC CLK P0-P7 TC CLK P0-P7 TC CLK P0-P7 TC E101 E101 CLOCK Figure 1. 32-Bit Cascaded E016 Counter 5 Micrel SY10E016 SY100E016 Programmable Divider The E016 has been designed with a control pin which makes it ideal for use as an 8-bit programmable divider. The TCLD pin (load on terminal count), when asserted, reloads the data present at the parallel input pin (Pn's) upon reaching terminal count (an all 1s state on the outputs). Because this feedback is built internal to the chip, the programmable division operation will run at very nearly the same frequency as the maximum counting frequency of the device. Figure 2 below illustrates the input conditions necessary for utilizing the E016 as a programmable divider set up to divide by 113. To determine what value to load into the device to accomplish the desired division, the designer simply subtracts the binary equivalent of the desired divide ratio for the binary value for 256. As an example for a divide ration of 113: PN's = 256 - 113 = 8F16 = 1000 1111 where P0 = LSB and P7 = MSB Forcing this input condition, as per the set-up in Figure 2, will result in the waveforms of Figure 3. Note that the TC output H P7 H L H PE CE TCLD CLK Q7 L P6 L P5 L P4 H P3 H P2 H P1 H P0 TC Q6 Q5 Q4 Q3 Q2 Q1 Q0 Figure 2. Mod 2 to 256 Programmable Divider LOAD CLOCK 1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111 LOAD PE TC Divide by 113 Figure 3. Divide by 113 E016 Programmable Divider Waveforms 6 Micrel Divide Ratio 2 3 4 5 Preset Data Inputs P4 P3 H H H H H H H H SY10E016 SY100E016 P7 H H H H P6 H H H H P5 H H H H P2 H H H L P1 H L L H P0 L H L H * * 112 113 114 * * H H H * * L L L * * L L L * * H L L * * L H H * * L H H * * L H H * * L H L * * 254 255 256 * * L L L * * L L L * * L L L * * L L L * * L L L * * L L L * * H L L * * L H L Table 1. Preset Values for Various Divide Ratios is used as the divide output and the pulse duration is equal to a full clock period. For even divide ratios twice the desired divide ratio can be loaded into the E016 and the TC output can feed the clock input of a toggle flip-flop to create a signal divided as desired with a 50% duty cycle. A single E016 can be used to divide by any ratio from 2 to 256, inclusive. If divide ratios of greater than 256 are needed, multiple E016s can be cascaded in a manner similar to that already discussed. When E016s are cascaded to build larger dividers, the TCLD pin will no longer provide a means for loading on terminal count. Because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the TC pins must be used for multiple E016 divider chains. Figure 4 on the following page shows a typical block diagram of a 32-bit divider chain. Once again, the maximize the frequency of operation, E101 OR gates were used. For lower frequency applications, a slower OR gate could replace the E101. Note that for a 16-bit divider, the OR function feeding the PE (program enable) input CANNOT be replaced by a wire OR tie as the TC output of the least significant E016 must also feed the CE input of the most significant E016. If the two TC outputs were OR tied, the cascaded count operation would not operate properly. Because in the cascaded form the PE feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device. Maximizing E016 Count Frequency The E016 device produces nine fast transitioning singleended outputs; thus, VCC noise can become significant in situations where all of the outputs switch simultaneously in the same direction. This VCC noise can negatively impact the maximum frequency of operation of the device. Since the device does not need to have the Q outputs terminated to count properly, it is recommended that, if the outputs are not going to be used in the rest of the system, they should be left unterminated. In addition, if only a subset of the Q outputs are used in the system, only those outputs should be terminated. Not terminating the unused outputs will not only cut down the VCC noise generated, but will also save in total system power dissipation. Following these guidelines will allow designers to either be more aggressive in their designs, or provide them 7 Micrel SY10E016 SY100E016 E101 Q0-Q7 "LO" CE PE CE Q0-Q7 PE CE Q0-Q7 PE CE Q0-Q7 PE E016 LSB E016 E016 E016 MSB CLK P0-P7 TC CLK P0-P7 TC E101 CLK P0-P7 TC E101 CLK P0-P7 TC CLOCK Figure 4. 32-Bit Cascaded E016 Programmable Divider PRODUCT ORDERING CODE Ordering Code SY10E016JC SY10E016JCTR SY100E016JC SY100E016JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial Ordering Code SY10E016JI SY10E016JITR SY100E016JI SY100E016JITR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Industiral Industrial Industrial Industrial 8 Micrel SY10E016 SY100E016 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 9 |
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